Secured Communication for Missile Navigation

In order to improve the security of the Military kinds of network this work is proposed. Here the position of missile navigates as per the user’s requirement. The user sends the co-ordinates through pc based server on the base station. For security purpose encryption is done with RC4algorithm implementation. The system that uses Human Computer Interaction and Visualization technology provides several encryption algorithms and key generators. Keywords— missile navigation, RC4 algorithm, VNC, PN sequence, USB, encryption INTRODUCTION In today’s world enemy warfare is an important factor of any nation’s security. The national security mainly depends on army (ground), navy (sea), air-force (air).The important and vital role is played by the army’s artillery such as scud missile, Bo force guns etc. As the name suggests we are making a secure Navigation of Missile using encryption based RC4 algorithm. This is done with the use of an encryption key. This encryption key specifies how the message is to be encoded. An authorized party is able to decode the cipher text using a decryption algorithm, which usually requires a secret decryption key that adversaries do not have access to. There are various types of encryption as AES, DES, and RC4 Algorithm etc. Encryption has long been used by militaries and governments to facilitate secret communication. An encryption based on chaos and AES algorithm [1]where the design and realization of an encryption system is based on the algorithm on ARM(S3C6410), which can encrypt and decrypt the information in many kinds of memorizers, such as UDisk, SD card and mobile HDD. The system that uses Human-Computer Interaction and Visualization technology provides several encryption algorithms and key generators. In this paper, they designed and implemented an encryption system to encrypt the stored data based on ARM (S3C6410). The PN sequences with good properties are generated from chaotic map and the system provides two kinds of encryption algorithm, one is stream cipher with XOR operation, the other is a hybrid algorithm of AES and chaos. In order to improve the security of the private information in memorizer, an encryption algorithm, which inherits the advantages of chaotic encryption, stream cipher and AES algorithm, is proposed in this paper. The chaotic selective encryption of compressed video (CS ECV) exploits the characteristics of the compressed video [2]. Encryption is needed to protect the multimedia data. Compared with text encryption; multimedia encryption has some unique characteristics, such as the large size, high throughput, and real-time processing. An efficient, secure, and lightweight encryption algorithm is desirable to protect the compressed video. A video clip is generally compressed in a transform Domain with some type of entropy coding. To protect a compressed video, encryption techniques can be applied to the original data, such as block swapping, or the data can be transformed using DCT or wavelet coefficients, entropy-coded bit streams, or format headers. The encryption has three separate layers that can be selected according to the security needs of the application and the processing capability of the client computer. The chaotic pseudo-random sequence generator used to generate the key-sequence to randomize the important fields in the compressed video stream has its parameters encrypted by an asymmetric cipher and placed into the stream. The resulting stream is still a valid video stream. CSECV has significant advantages over existing algorithms for security, decryption speed, implementation flexibility, and error preservation. The paper presents the design and implementation of a software application for the provision of secure real time communication services between workstations, based on the AES prototype cryptographic algorithm and an advanced secret key management system [3]. The application has been designed based on the requirements of a military unit, so as to allow groups of authenticated users to International Journal of Engineering Research and General Science Volume 2, Issue 4, June-July, 2014 ISSN 2091-2730 399 www.ijergs.org communicate and read the transmitted messages. This application can be used as the basis for the design of an integrated communication system for a military organization. The present design confines its operation within the limits of a local area network, but the possibilities are open for operation in extended networks or the internet. Advanced Encryption Standard (AES) is the most secure symmetric encryption technique that has gained worldwide acceptance. ―FPGA implementations of advanced Encryption standard: a survey‖ presents the AES based on the Rijndael Algorithm which is an efficient cryptographic technique that includes generation of ciphers for encryption and inverse ciphers for decryption[4]. Higher security and speed of encryption/decryption is ensured by operations like Sub Bytes (S-box)/Inv. (Inv.S-box), Mix Columns/Inv. Mix Columns and Key Scheduling. Extensive research has been conducted into development of S-box /Inv. S-Box and Mix Columns/Inv. Mix Columns on dedicated ASIC and FPGA to speed up the AES algorithm and to reduce circuit area. This is an attempt, to survey in detail, the work conducted in the aforesaid fields. The prime focus is on the FPGA implementations of optimized novel hardware architectures and algorithms. Fault attacks are powerful and efficient cryptanalysis techniques to find the secret key of the Advanced Encryption Standard (AES) algorithm [5]. The paper shows that these attacks are based on injecting faults into the structure of the AES to obtain the confidential information. To protect the AES implementation against these attacks, a number of counter measures have been proposed. In this paper, a fault detection scheme for the Advanced Encryption Standard is proposed. They present its details implementation in each transformation of the AES. The simulation results show that the fault coverage achieves 99.999% for the proposed scheme. Moreover, the proposed fault detection scheme has been implemented on Xilinx Virtex-5 FPGA. Its area overhead and frequency degradation have been compared and it is shown that the proposed scheme achieves a good performance in terms of area and frequency.